1. Technical Field
The present invention relates to a packaging method using a solder coating-ball and a package manufactured thereby.
2. Description of the Related Art
According to the prior art, a flip chip scheme in which a solder bump is formed on a printed circuit board (PCB) and then, a device is mounted thereon to thereby package them has been increasingly used.
In particular, in the case of a central processing unit (CPU) and a graphic operation device operating large capacity data at a high speed, a change from a scheme connecting between a substrate and a device using a gold (Au) wire according to the prior art to the flip chip scheme in which the substrate and the device are connected by the solder bump so as to improve connection resistance has been rapidly increased.
Methods forming the solder bump as described above may be divided into a scheme forming the solder bump by printing a solder paste on the substrate and then reflowing the solder paste, a scheme forming the solder ball by mounting a fine solder ball on the substrate, and a method forming the solder bump by injecting a melted solder into the substrate directly or using a mask. The solder bump formed on the substrate as described above is melted so as to connect to a copper (Cu) pad or a solder bump formed on a chip, thereby coupling between metals.
The methods forming the above-mentioned solder bump may include a ball placing scheme in which the same size openings having the same size are formed on the mask and then the solder ball is squeegeed using a squeegee, such that the solder ball is mounted on input/output pad of the substrate through the mask openings, or a scheme in which a vacuum hole having the same pattern as a substrate pattern is formed at a jig and then the solder ball is picked-up at vacuum so as to be mounted on the substrate, as described in Korea Patent Laid-Open Publication No. 2008-0014143 (laid-open published on Feb. 13, 2008).
However, as a pitch of the input/output pad of the substrate gradually becomes fine, a technology forming the solder bump on the input/output pad of the substrate using the solder ball or a paste according to the prior art has been gradually changed to a scheme forming the bump made of copper (Cu) using a plating and lithography technologies.
The packaging method using the bump made of copper (Cu) using the above-mentioned plating and lithography technologies has a problem in that an interface between the solder and an electroless Cu is separated from each other due to low interface stability, such that processing stability is degraded.
In addition, a plating thickness deviation occurring at the time of plating copper (Cu) leads to a height deviation between the solder and the copper (Cu) bump, such that connection reliability in the packaged chip is deteriorated.